Inductive structure integrated on a semiconductor substrate

ABSTRACT

An inductive structure integrated in a semiconductor substrate, comprising at least a conductive element insulated from the substrate, comprising an insulating structure, which is formed inside said semiconductor substrate and built close to said conductor element, so that the resistance of said substrate is increased and the parasitic currents induced by the conductor element in the substrate are decreased. The insulating structure including a plurality of insulating elements each surrounding a respective one of a plurality of semiconductor islands of the substrate.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to an inductive structure integrated in a semiconductor substrate.

[0003] The invention specifically concerns an inductive structure integrated in a semiconductor substrate, comprising at least an conductive element on the substrate.

[0004] Particularly, but not exclusively, the invention relates to an inductor that is integrated into a SOI (Silicon On Insulator) technology and the following description is made with reference to this application field with the only aim to simplify its explanation.

[0005] 2. Description of the Related Art

[0006] As it is well known, inductors are the most difficult to form in integrated circuits among all the passive electric devices (resistors, capacitors and inductors). In fact, the integrated realization of the inductors requires areas and volumes rather large on silicon, in order to reach the conventionally used inductance values.

[0007] A first solution of the prior art to form inductors having high inductance values is the one of forming some planar coils into the semiconductor substrate. It is possible to reach the desired inductance value by forming a proper number of coils.

[0008] A second problem, one that appears during the integration of the inductors is the one of obtaining a high quality factor (Q).

[0009] In fact, because of the magnetic field associated with the inductance that is integrated into the substrate, parasitic phenomena occur and cause a decrease of the inductance efficiency.

[0010] Particularly, Foucault currents which are generated in the silicon substrate tend to counterbalance the magnetic field generated by the current circulating in the inductance.

[0011] A solution useful to decrease the influence of such currents is to increase the substrate resistivity.

BRIEF SUMMARY OF THE INVENTION

[0012] An embodiment of the present invention is directed to an inductive structure with a high value of the quality factor, which has structural features such to reduce the parasitic currents induced in the substrate, thereby overcoming the limitations that to now are limiting the inductive structures built according to the prior art.

[0013] The insulating structure includes a plurality of trench portions formed in a semiconductor substrate and filled with insulating material; and an inductor formed over the insulating structure. The trench portions each surround a respective one of a plurality of semiconductor islands of the substrate.

[0014] The features and the advantages of the structure according to the invention will be apparent from the following description of a preferred embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0015] In such drawings:

[0016]FIG. 1 shows a vertical cross sectional view of a first embodiment of an inductive structure according to the invention;

[0017]FIG. 2 shows a top view of a second embodiment of an inductive structure according to the invention;

[0018]FIG. 3 shows a top view of a third embodiment of an inductive structure according to the invention;

[0019]FIG. 4 shows an enlarged scale top view of a substrate portion of the third embodiment of the inductive structure according to the invention;

[0020]FIG. 5 shows a comparative diagram between three inductive structures of the prior art and the embodiments according to the invention;

[0021]FIG. 6 shows a picture of a substrate portion of the inductive structure according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0022] With reference to such figures, an inductive structure 1 schematically shown that is formed using a semiconductor substrate 2, such as a silicon substrate for example.

[0023] The figures show schematic views of some portions of an integrated circuit and are not drawn in scale, but are instead drawn in a way such that the important features of the invention are shown.

[0024] The inductive structure 1 comprises an electric conductor 3, which is an inductor patterned like a spiral in order to obtain the desired inductance value. The inductor 3 is positioned on the substrate 2 and is insulated from the substrate by a thin insulating layer 7.

[0025] According to an embodiment of the invention, in the substrate 2 at least one insulating structure 4 is formed.

[0026] In a first embodiment, such an insulating structure 4 is formed with SOI (Silicon on Insulator) technology. Using SOI technology, the substrate 2 is formed by bonding together a first substrate 2 a, covered with an oxide layer 5, and a second substrate 2 b, so that the oxide layer 5 remains buried between the first and the second substrate, as shown in FIG. 1.

[0027] The domain in which the Foucault currents can flow is limited by forming the inductor 3 on the surface of the second substrate 2 b. In such a way the domain is limited and the risk of cross-coupling among different stages of electronic circuits, which are possibly present in the substrate, is eliminated.

[0028] As shown in FIG. 2, the insulating structure 4 includes an array of insulating elements 6 in the semiconductor substrate 2 which are formed in order to increase the equivalent resistance under the inductor 3.

[0029] Such elements 6 can be formed through trenches etched in the semiconductor substrate 2 and filled with an insulating material, such as oxide for example.

[0030] Such insulating elements 6 can have a substantially cylindrical shape, with a round or multipolygonal profile, and deeply extend in the substrate 2 and delimit silicon islands or semiconductor elements 2 c. In such a way the induced magnetic field, which is associated to the Foucault currents provided in the substrate 2, is reduced.

[0031] There is nothing to prevent such insulating elements 6 also having a cross sectional annular or ring-like shape, which deeply extends in the substrate 2.

[0032] The total insulating structure 4 comprises a matrix of insulating elements 6, which can be formed in a portion or all of the substrate 2 on which the inductor is formed.

[0033] An improved effect is obtained if the insulating elements 6 are linked with each other by insulating linking elements 6 a, as is shown in FIGS. 3 and 4.

[0034] For example, the cylindrical structures 6 made out of insulating material can be formed in the substrate 2, which are connected to each other by the insulating linking elements 6 a, so that a maze is formed.

[0035] The insulating elements 6 are substantially placed in a network with regular structure.

[0036] In such a way the plurality of silicon domains 2 c are produced, such domains being electrically insulated from each other. In this way each domain 2 c will develop a Foucault current in an opposite direction to the current which flows in the inductance. Each domain 2 c is surrounded by other insulated domains 2 c and the reverse field effect of each of them will be cancelled by the surrounding domains 2 c (having the same order of magnitude but on adjacent faces with opposite direction).

[0037] In summary, the inductive structure 1 is formed on a portion of substrate 2, which comprises a plurality of semiconductor elements 2 c that are separated from each other by at least a trench made in the semiconductor 2, such at least a trench being filled with insulating material so that said plurality of semiconductor elements 2 c are at least partially insulated from each other by the insulating elements 6 and the linking elements 6 a.

[0038] In other words, the substrate portion under the inductor 3 is substantially shaped as mosaic tiles 2 c insulated from each other by a trench filled with insulating material, so that the parasitic currents induced into the substrate by the inductor 3 are reduced.

[0039] The graph of FIG. 5 shows a comparative diagram reporting the pattern of the quality factor in function of the frequency of use for an integrate inductor of the known type and according to the present invention.

[0040] Particularly, the curve A shows the pattern of the quality factor in function of the frequency for inductors formed according to the prior art, the curve B shows the pattern of the quality factor in function of the frequency for inductors formed according to the embodiment of FIG. 2, and the curve C shows the pattern of the quality factor in function of the frequency for inductors formed according to the embodiment of FIG. 3.

[0041] As it can be appreciated, the testing data also confirms the improvement of the quality factor of inductors formed according to the invention.

[0042] It is clear that the insulating structures according to the invention can be formed in a simple substrate or in a SOI technology one.

[0043] When the structures according to the invention are formed in a SOI technology, the resistive effect will be further increased if the insulating elements 6 contact the buried oxide layer 5.

[0044] The process for forming the inductive structure 1 in a semiconductor substrate will be now described.

[0045] However, the hereafter described process steps do not form a complete process flow for manufacturing integrated circuits. The present invention can be put into practice together with integrated structure manufacturing techniques presently used in the field, and only those commonly used process steps that are necessary for the understanding of the present invention are included.

[0046] In a semiconductor substrate 2, for example with a conductivity of the P type, a layer of photosensitive material is laid, in which a mask is defined by means of conventional photholitographic processes.

[0047] In such a mask the geometry of the insulating structure 4 of the inductive structure 1 is defined.

[0048] Therefore, an etching phase of the semiconductor substrate 2 a occurs so that the plurality of semiconductor elements 2 c separated from each other by trenches 8 formed in such substrate 2 a is obtained.

[0049]FIG. 6 is a picture, which is made with the electronic microscope, showing a portion of the substrate 2 a of the embodiment of FIG. 3, at the end of such etching phase.

[0050] Once the mask is removed, an oxide layer is formed inside the trenches made in the substrate in order to form the insulating elements 6 and linking elements 6 a of the insulating structure 4.

[0051] The insulating elements 6 are placed in reciprocal spaced positions and put in the substrate 2 according to a matrix.

[0052] Such elements 6 can substantially have an annular cross-section shape.

[0053] In a further embodiment of the invention, such elements 6 are connected to each other by the linking elements 6 a in order to form an insulating structure as a regular lattice.

[0054] In such a case, the shape of each element can be an annular one. There is nothing to prevent such insulating elements 6 from having a different shape.

[0055] The process is therefore completed by means of conventional process steps that comprise:

[0056] the formation of the oxide layer 5 on the substrate portion where the insulating structure 4 is formed;

[0057] the formation of the second substrate layer 2 b on the oxide layer 5;

[0058] the formation of the thin insulating layer 7, which may be oxide or other insulating material; and

[0059] the formation of the inductor 3 through a first or a second metalization layer.

[0060] The shape of such inductor depends on the desired inductance value.

[0061] As it has been said, there is nothing to prevent such inductive structures 1 being formed without the SOI technology, and, therefore for such process phases to be activated on a unitary substrate without the intervening oxide layer 5. In addition, the inductor 3 could be formed directly on the substrate 2 without the insulating layer 7.

[0062] From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims. 

I claim:
 1. An inductive structure integrated in a semiconductor substrate, comprising: a conductive elementformed on the substrate; and an insulating structure built inside said semiconductor substrate and in correspondence with said conductive element, in order to increase the resistance of said substrate and decrease the parasitic currents, which are induced in the substrate by the conductive element, the insulating structure including a plurality of insulating elements each surrounding a respective one of a plurality of semiconductor islands of the substrate.
 2. The inductive structure integrated in a semiconductor substrate according to claim 1, wherein said insulating structure includes an insulating layer formed between the insulating elements and the conductive element.
 3. The inductive structure integrated in a semiconductor substrate according to claim 1, wherein said insulating elements are substantially cylindrical.
 4. The inductive structure integrated in a semiconductor substrate according to claim 1, wherein the conductive element is shaped in a spiral pattern.
 5. The inductive structure integrated in a semiconductor substrate according to claim 1 wherein said insulating elements are separated from each other by portions of the substrate.
 6. The inductive structure integrated in a semiconductor substrate according to claim 1 wherein said insulating elements are interconnected with each other by insulating connectors.
 7. The inductive structure integrated in a semiconductor substrate according to claim 1 wherein the substrate is an SOI substrate that includes first and second substrate portions, the substrate islands being part of the first substrate portion, the second substrate portion being positioned on the first substrate portion, and the conductive element being formed on the second substrate portion.
 8. A method to form inductive structures on a semiconductor substrate, comprising the following phases: depositing a layer of photosensitive material on the semiconductor substrate; defining a mask in said layer of photosensitive material by conventional photolithographic processes; etching the semiconductor substrate through the mask in order to form trench portions in the substrate, each trench portion surrounding a respective one of a plurality of semiconductor islands of the semiconductor substrate; filling said trench portions with insulating material in order to insulate the semiconductor islands from each other and to form an insulating structure; forming a conductive inductor element on the semiconductor substrate and aligned with least one portion of the said inductive structure in order to reduce the parasitic currents induced by the inductor element in the substrate.
 9. The method of clam 8, further comprising forming an insulating layer one the insulating structure and below the inductor element.
 10. The method of claim 8 wherein the trench portions are substantially cylindrical.
 11. The method of claim 8 wherein the trench portions are separated from each other by portions of the substrate.
 12. The method of claim 8 wherein the trench portions are part of a single trench such that the trench portions are interconnected with each other.
 13. The method of claim 8, further comprising forming a semiconductor layer on the insulating structure and below the inductor element. 